1. Field of the Invention
The present invention relates to a delay circuit, in particular, a delay circuit to prevent current from flowing through a driver circuit.
2. Description of Related Art
A driver circuit to drive a load such as a motor is conventionally equipped with a delay circuit to prevent current from flowing through the driver circuit. FIG. 4 shows a driver circuit 400 in related art. The driver circuit 400 includes a through current prevention circuit 401 composed of delay circuits 402a and 402b and inverters INV1 and INV2, and CMOS transistors (a PMOS transistor P1 and a NMOS transistor N1). The CMOS transistors are connected to the through current prevention circuit 401, and connected between power supply potential and ground potential. Furthermore, a load such as motor (not shown) is connected to the output OUT of the CMOS transistors.
The delay circuit 402a outputs a delayed signal, the rising edge of which is delayed from the rising edge of the input signal IN supplied through the inverter INV1 (see output of delay circuit 402a in FIG. 5). Furthermore, the delay circuit 402b outputs a delayed signal, the rising edge of which is delayed from the rising edge of the input signal IN (see output of delay circuit 402b in FIG. 5). When the first delayed signal in “High” level, which is outputted from the inverter INV2, is inputted to the gate of the PMOS transistor P1, the PMOS transistor P1 becomes the off-state. Meanwhile, the second delayed signal in “Low” level is inputted to the gate of the NMOS transistor N1, the NMOS transistor N1 is in the off-state. That is, the driver circuit 400 creates the situation where both of the PMOS transistor P1 and NMOS transistor N1 become the off-state at the same time by the delay circuits 402a and 402b (see t1-t2 and t3-t4 in FIG. 5), and thereby preventing through current from the power supply potential VDD to the ground potential, which may otherwise occur when both of the PMOS transistor P1 and NMOS transistor N1 become the on-state at the same time.
FIG. 6 shows internal structure of a delay circuit 402 in the related art. The delay circuit 402 is composed of a plurality of rising edge delay circuits 403 connected with one another. Each of the rising edge delay circuits 403 creates desired delay time by, for example, connecting several invertors, each of which is composed of a PMOS transistor and a NMOS transistor (see FIG. 7).
Japanese Unexamined Patent Publication No. 10-13207 discloses a delay circuit (through current prevention circuit) to generate desired delay time by controlling the operations of several flip-flop circuits connected with one another based on a clock signal supplied to an external clock input terminal CK (see FIG. 8).
However, in the delay circuit in FIG. 6, for example, there may be variations (or deviations from the desired value) in the final delay time among the devices. That is, transistors in the plurality of rising edge delay circuits 403a-403n may have process variations caused in the manufacturing process. Consequently, the rising edge delay circuits 403 may have variations in their delay times among each other. Therefore, delay circuits in the related art have variations (or deviations from the desired value) in the final delay time.